This invention relates to an automatic test equipment for testing semiconductor devices for supplying test pattern signals to a semiconductor device and evaluating resultant output signals of the semiconductor device, and more particularly, to an event based semiconductor test system for producing events of various timings to be used as test pattern signals and strobe signals to evaluate semiconductor devices wherein the timing of each of the events is defined by a time length from a predetermined point.
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor device to be tested is provided with test signals at its appropriate pins with predetermined test timings. The semiconductor test system receives output signals from the device under test generated in response to the test signals. The output signals are sampled by strobe signals with specified timings to be compared with expected value data to determine whether the semiconductor device under test functions correctly or not.
FIG. 1 is a schematic block diagram showing an example of a conventional semiconductor test system. In the semiconductor test system of FIG. 1, a pattern generator 12 receives test data from a test processor 11. The pattern generator 12 generates test pattern data to be provided to a wave formatter 14 and an expected value pattern to be provided to a pattern comparator 17. A timing generator 13 generates timing signals to synchronize the operation of the overall test system. In FIG. 1, the timing signals are provided, for example, to the pattern generator 12, the pattern comparator 17, the wave formatter 14, and an analog comparator 16.
The timing generator 13 also provides a test cycle (tester rate) pulse and timing data to the wave formatter 14. The pattern (test vector) data defines xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, i.e., rising and falling edges of the test signal waveform. The timing data (timing set data) defines timings (delay times) of the rising and falling edges of the waveform relative to the test cycle pulse. Typically, the timing data also includes waveform information such as an RZ (return to zero), NRZ (non-return to zero) or EOR (exclusive OR) waveform.
Based on the pattern data from the pattern generator 12 and the test cycle pulse and timing data from the timing generator 13, the wave formatter 14 forms a test signal having specified waveforms and timings. The wave formatter 14 sends the test signal to the DUT 19 through a driver 15. The wave formatter 4 includes set/reset flip-flops (not shown) to form the test signal to be provided to the driver 15. The driver 15 regulates the amplitude, impedance, and/or slew rate of the test signal and applies the test signal to the DUT 19.
A response signal from the DUT 19 is compared with a reference voltage at a predetermined strobe timing by the analog comparator 16. The resultant logic signal is provided to the pattern comparator 17 wherein a logic comparison is performed between the resultant logic pattern from the analog comparator 16 and the expected value pattern from the pattern generator 12. The pattern comparator 17 checks whether two patterns match with each other or not, thereby determining pass or failure of the DUT 19. When a failure is detected, such failure information is provided to a fail memory 18 and is stored along with the information of the failure address of the DUT 19 from the pattern generator 12 in order to perform failure analysis.
In the conventional semiconductor test system such as shown in FIG. 1, a test signal to be applied to the device under test is produced in a cycle by cycle manner based on three kinds of data, pattern (vector) data, timing data and waveform data. FIG. 2 shows an example of relationship among the three kinds of data as well as the test cycle to generate test signals shown in waveform illustration 45. Pattern data (test vector) 46 from a test vector file 41 is provided to the wave formatter 14 through the pattern generator 12. Timing data 47 from a test plan file 42 is provided to the wave formatter 14 through the timing generator 14. The pattern data 46 defines edges (1 or 0) in each test cycle and the timing data 47 defines waveforms and timings, i.e., delay time relative to the test cycle.
As noted above, in the conventional semiconductor test system, the test signals and strobe signals are produced based on the pattern data, timing data and waveform data relative to each test cycle. Such a test system is sometimes called a cycle based test system in which timing data and pattern data are described in a cycle by cycle basis. In computer aided design (CAD) systems widely used today for designing a semiconductor device such as an LSI and VLSI, typical logic simulators describe test signals and results based on event basis. Events are any changes in the logic state, such as rising and falling edges of test signals and are defined with respect to time lengths from a reference time point. In other words, event based description of test signals and test results does not utilize the idea of test cycles used in the conventional test system. Therefore, the conventional cycle based test system cannot make direct use of the test signals and test results obtained in the design stage of the semiconductor devices.
Therefore, it is an object of the present invention to provide an event based semiconductor test system for producing test signals and test strobes directly from event data in an event memory to evaluate a semiconductor device.
It is another object of the present invention to provide an event based semiconductor test system wherein the timing of each of the events is defined by a time length from a predetermined reference point.
It is a further object of the present invention to provide an event based semiconductor test system wherein the timing of each of the events is defined by a time length from the last event.
It is a further object of the present invention to provide an event based semiconductor test system in which a time length between events is defined by a combination of an integer multiple of a reference clock cycle and a fraction of the reference clock cycle.
It is a further object of the present invention to provide an event based semiconductor test system which is capable of scaling the timing data for producing the current events by modifying the delay times of the current events in proportion to a scaling factor.
It is a further object of the present invention to provide an event based semiconductor test system incorporating a data compression and decompression technology for storing event data in an event memory for decreasing a capacity of the event memory.
It is a further object of the present invention to provide an event based semiconductor test system which is capable of directly using data produced by a test bench of a CAD system in a design stage of the semiconductor device under test for generating test signals and strobes.
The present invention is an event based test system for testing an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes: an event memory for storing timing data of each event formed with an integer multiple of a reference clock period (integral part data) and a fraction of the reference clock period (fractional part data) wherein the timing data represents a time difference between a current event and a common reference point, an address sequencer for generating address data for accessing the event memory to read out the timing data therefrom, a timing count and scaling logic for generating an event start signal which is delayed by the reference clock period multiplied with the integral part data, an event generation unit for generating each event based on the event start signal from the timing count and scaling logic and the fractional part data from the event memory for formulating the test signal or strobe signals, and a host computer for controlling an overall operation of the event based test system through a test program.
In a further aspect of the present invention, the event memory is comprised of a clock count memory for storing the integral part data of the timing data of each event, a vernier memory for storing the fractional part data of the timing data of each event, and an event type memory for storing data representing a type of each event corresponding to the timing data in the clock count memory and the vernier count memory.
In a further aspect of the present invention, the event based test system further includes a decompression unit between the event memory and the timing count and scaling logic for reproducing event data from compressed event data stored in the event memory, and the timing count and scaling logic includes a scaling function which modifies the event data from the event memory in proportion to a scaling factor.
In a further aspect of the present invention, the event generation unit is comprised of a demultiplexer for selectively providing the event start signal from the timing count and scaling logic based on event type data from the event memory, a plurality of variable delay circuits for receiving the event start signal from the demultiplexer where each of the variable delay circuits provides an additional delay defined by vernier sum data from the timing count and scaling logic, means for producing variable offset delay between test signals.
According to the present invention, an event based semiconductor test system is capable of producing test signals and strobes based on the event data stored in the event memory to evaluate a semiconductor device. The timing of each of the events is defined by a difference of time length from the common reference point (absolute time) or from the last event (delta time). The test signals and strobes are produced based on event information whose delta time from the previous event is defined by a combination of an integer multiple of the reference clock period and a fraction of the reference clock period.